Camouflage Design/Analysis Tool
To mitigate Reverse Engineering on ASICs, we offer Camouflage Design/Analysis Tool to provide camouflage cells replacement in a netlist and to analyse the security level of the camouflaged netlist.
Camouflaged netlist generation to prevent from netlist analysis
Simple design flow (compatible with commercial design flows)
Graphical-user-interface – easy for use
Options for power/area/speed trade-offs
Comprehensive analysis report
Technical support available