Design and Analysis Tools

We offer three Design & Evaluation Tools as follows:


Side-Channel Attack (SCA) Evaluation Tool & FPGA Evaluation Boards

To perform efficient SCA evaluations on Advanced Encryption Standard (AES) designs on the basis of simulations or measurements, we offer a user-friendly SCA Evaluation Tool. FPGA evaluation boards are available for AES implementations and their SCA evaluations.



KEY FEATURES

Graphical-User-Interface (GUI)

Ease of Use

Fast analysis and pre-qualification

Applicable to AES

Applicable to both simulation & measurement data

SCA for power and electromagnetic (EM) method

State-of-the art attacks – Correlation Power Analysis, Differential Power Analysis, and Machine Learning

Configurable points of attack

Configurable power models (Hamming Weight, Hamming Distance, Weight Model, Bit Model, Zero Model, etc.)

Trace management

Pre-analysing, pre-processing and digital signal processing features available

Data acquisition possible

FPGA hardware evaluation board available

Trace management

Technical support available


For more information, please download our product brochures as follows.

Brochure for the SCA Evaluation Platform

Brochure for the FPGA Evaluation Boards


Camouflage Design/Analysis Tool

To mitigate Reverse Engineering on ASICs, we offer Camouflage Design/Analysis Tool to provide camouflage cells replacement in a netlist and to analyse the security level of the camouflaged netlist.


KEY FEATURES

Camouflaged netlist generation to prevent from netlist analysis

Simple design flow (compatible with commercial design flows)

Graphical-user-interface – easy for use

Options for power/area/speed trade-offs

Comprehensive analysis report

Technical support available


Asynchronous-logic Design Tool

To provide the design solution for asynchronous-logic in netlist level, we offer Asynchronous- logic Design Tool with high compatibility of standard design flow.


KEY FEATURES

Single-rail to dual-rail conversion

Dual-rail logic implementation

Self-timed handshake operation

Applicable to FPGA/ASIC

Optimization for power/area/speed